1. Field of the Invention
The present invention relates to a semiconductor device. Particularly, the present invention relates to a semiconductor device including a capacitor as a memory element.
Priority is claimed on Japanese Patent Application No. 2009-210472, filed Sep. 11, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, the area of each element forming a semiconductor device has been reduced with the miniaturization of semiconductor devices. Regarding DRAM (Dynamic Random Access Memory) including a memory cell portion and a peripheral circuit portion, the area of the memory cell portion is being reduced. A crown-shaped capacitor has been proposed in order to achieve sufficient capacitance of a capacitor forming a memory cell portion.
Capacitor structures have been complicated in order to achieve higher capacitance. For example, Japanese Patent Laid-Open Publication No. 2004-311918 discloses a capacitor, which includes stacked lower electrodes that are a first lower electrode and a second lower electrode on the first lower electrode. The first lower electrode is cylindrical, and the second lower electrode is crown-shaped, thereby achieving sufficient capacitance and enabling a reduction in defects at the time of a dry etching process.
As a capacitor including stacked lower electrodes, Japanese Patent Laid-Open Publication No. 2004-72078 discloses a capacitor, which includes stacked lower electrodes that are a lower storage electrode and an upper storage electrode on the lower storage electrode. Japanese Patent Laid-Open Publication No. 2002-313952 discloses a capacitor having a stacked cylindrical structure, which is formed by repeating a process of forming a hole in an inter-layer insulating film and a process of forming an electrode covering an inner surface of the hole.
As a method of simultaneously etching a capacitor including stacked lower electrodes, Japanese Patent Laid-Open Publication No. H09-191084 discloses a method including a process of forming a first inter-layer insulating film and a second inter-layer insulating film on the first inter-layer insulating film, and a process of forming first and second holes penetrating the first and second inter-layer insulating films, respectively. The first and second diameters of the first and second holes are changed so that first and second etching rates of the first and second inter-layer insulating films are changed, thereby enabling formation of the capacitor including stacked lower electrodes in one process.
However, if the allowable area of a plan region in which a capacitor is formed is reduced with the miniaturization of semiconductor elements, even the capacitor structure disclosed in Japanese Patent Laid-Open Publication No. 2004-311918 cannot achieve a predetermined capacitance. Further, if the aspect ratio of the capacitor increases, regardless of whether the lower electrode is cylindrical or crown-shaped, mechanical strength of the lower electrode decreases, thereby causing the lower electrode to collapse. Moreover, the contact area between the first lower electrode and the second lower electrode on the first lower electrode decreases, thereby increasing contact resistance, and therefore causing a degradation of characteristics of the capacitor as a memory element.